IBM LAN Entry Programmer's Guide

IBM made, for a while, a card called the IBM LAN Entry card. This card has made its way to the surpluss market and can be purchased cheaply (in the $25-$35 range) from surplus dealers. More information can be obtained from here. Drivers can be obtained from here. I recommend Kento for purchasing one of these cards. I've dealt with him any times and he's A-1. Also of interest is Anthony M Townsend's page. The cards have a part number of either 92G7787 or 13H5905 depending on where you look.

Since this is a cheap, wireless card, the desire has been strong to have drivers written for this card for FreeBSD, Windows NT, Linux and other operating systems. This document attempts to describe the register set and software interface to this card.

In this document, active low lines are represented with a trailing star (*). The Intel data sheets have them as an overbar, but I don't know how to do that in HTML. When quoting other documentes, I use elipsis (...) to indicate omitted material. Editorial or summary comments appear like this.

This is a work in progress. Please contribute what you can to it.

Card architecture

CPU --- PCMCIA BRDIGE --- PCMCIA BUS --- 
      CUSTOM ASIC CONTROLLER +-- Radio
                             |
                             +-- i593


BLOCK DIAGRAM

Custom ASIC

Intel 82593

Memory

Radio

Register Summary

Detailed register description

Excerpts from Intel datasheets

i593 Internal Architecture

Parallel Subsystem

The BIU is composed of two I/O ports, Port 0 through which time-critical tasks and configurations are executed and Port 1, which is used for auxiliary commands. The 8-bit Port 0 command and statis registers are interfaced to the CPU via the data lines D0-D7. Operation and initialization commands such as TRANSMIT, RCV-ENABLE and CONFIGURE are issued to the 82593 via the Port 0 Command Register. The resultant status of these commands, as well as the states (Idle, Active, Ready, etc) of the 82593's RCV and EXEC units are contained in the Port 0 Status Registers.

Port 1 command and status registers are also 8 bits wide. The Port1 Command Register is used for additional commands such as POWER-DOWN and STOP-REG-UPDATET. The port 1 status registers, Status Bank 1, contain the values of the Bus Throttle Timer, the RCV Stop Register and the Power Down and Hi-Impedance status It appears that the Power Down and Hi-Z stuff isn't used on the ILE cards. At least the DOS NDIS driver never touches those values.

The DUI is compiosed of two separate DMA channels, Channel 0 and Channel 1. ... The DMA channels are 8 bits wide (configurable to 16 bits). The two DMA channels are independent of each other. Both channels can request DMA services simultaneously for operations such as transmission and reception.

Dedicated logic in the DIU enables back-to-back transmition and reception when configured to Continuous Mode. This means that continuous transmissions and receptions can be hanled by the 82593 without real time intervention of the CPU. In this mode, the DRQ and EOP* pins can be used to discriminate between successful and unsuccessful operations.

The Bus Timer Throttle controls the maximum amount of time the 82593 can actively hold the bus (via the DMA controller) during a DMA cycle... The NDIS DOS driver doesn't set this value at all, rather it allows it to remain the default.

Serial Subsystem

The programmable parameters include:

• Address Field Length
• Station Priority (Linear and Exponential Priority)
• Interframe Spacing
• Slot Time
• CRC-32 or CRC-16
• Preamble Length

The CSMS/CD unitis capableofrunning at speedsfrom dc to 20Mb/s for the S82593, and dc to 16Mb/s for the 82593SX.

The 82593 detects a collision when an active signal is driven on its CDT*/CLSN input. This signal is usually driven from the serial itnerface device ... It detects a carrier on the link when an active signal is driven on its CRS*/RENA input. The 82593 can be configured to filter active for at least 1 to 7 TXC periods before it is recognized.

FIFO Subsystem

When configured to its 82590 compatible mode, the 82593 FIFO length defaults to 32 bytes for both the RCV and XMT FIFO, and the FIFO threshold (the level where a DMA request is asserted or deasserted) is fixed at 16 bytes. In all other configurations, the FIFO length is 96 bytes, with the FIFO threshold programmable through configuration. The 82593 can also be configured to delay the start of transmission until the programmed XMT FIFO threshold has been reached.

Expansion of XMT FIFO to 96 bytes allows the 82593 to perform automatic transmissions from within the XMT FIFO when a collision occurs during transmission.

Programming model Register Overview

Port 0

The 82593 can be configured to have 4 or 6 bytes of status registers in Port 0 (see Figures 5, 6, and 7). For the 4-byte status configuration, the first the registers (STATUS 0 through 2) contain the inforamtion about the last command executed, or the last frame received. The last stauts register, STATUS 3, contains the state of the 82593 Execution and Receive units. When the 82593 is configured to 6 bytes of status registers, the two additional bytes of status are used to report a more complete stauts of the most recently receieved frame, and also transmit chaining status (Continuous mode only).

Port 1

The Port 1 status registers are called Status Bank 1. The three registers contained in Status Bank 1 are shown in Figure 11. Status Bank 1 holds the value of the Stop Register, the Bus Throttle Timer, and the power down and high impedance states.

82593 and host cpu interaction

Prior to issuing a parametric command to the 82593, the CPU creats a data structure in memory, and programs the external controller with the start address and byte count of the memory block. The ILE's ASIC is the CPU for the purposes of this paragraph. To initiate a parametric command, copy the data structure to the card memory. Then tell the ASIC which DMA channel to use. Issue the command to the '593. For commands that require no transfer of parameters to the 83593 ... the CPU issues the command to the device without creating a data structure in memory. The 82593 performs the command with no further involvement from the CPU. Any parameters or data assicauted with the command are transferred between the memory and the 82593 by the DMA controller eg the ASIC. Upon completion of the operation, the 82593 updates the appropriate status registers and asserts its INT line to the CPU The INT line is routed by the ASIC to the pcmcia bus's interrupt pin. The ASIC multiplexes the interupt with other radio events .

Frame Transmission

Transmit Frame Chaining

Following a successful transmission, the 82593 requests the command byte which follows the last data byte of a frame. EOP* is asserted druing this cycle, indicating a successful transmission. Assertion of EOP* in this mode can also be disabled.

If the command byte contains the TRANSMIT opcode, the 82593 will behave as if another TRANSMIT command has been issued by the CPU, and will attempt to trasmit the new frame as soon as deferring is completed. A NOP in the command byte indicates that the preceing frame was the last frame to be transmitted and no other frames follow.