Memory address convention (for this FAQ), and the GPRs

There is a certain amount of confusion about memory addressing representation due to the fact that the PDP-11 was originally launched with 16-bit addressing, but was extended through 18-bit to 22-bit over time.

On the 11/20, the processor status word (PSW), the topmost addressable location, would have address 177776, while on the 11/40 the address would be 777776, and on the 11/70, 17777776. Of course the hardware also helped in bit extending for you if you toggled in 177776 in an 11/70....

For the purposes of this FAQ I propose to take the middle ground and refer to addresses as if we were talking about an 11/40. Make your mental adjustments as appropriate.

There is one further area of confusion. Addresses are byte aligned, with an even address referring to a word (unless this is a byte operation in which case the lower byte of the word is the target) and an odd address specifying the upper byte of the word. In English, memory locations are incremented up in steps of 2.

There is, of course, an exception. The General Purpose Registers (GPRs) had addresses that incremented in steps of 1. R0 is 777700, R1 is 777701 .. R6(Kernel) is 777706, R7(Kernel) is 777707. Later models had a second set of GPRs at 777710 through 777717. The complication does not stop here, though. The Kernel Stack pointer (SP) is at 777706, the supervisor SP at 777716 and the User SP is at 777717.

It should be noted that using memory addresses to get at the registers is not supported by the LSI-11 chip sets. This applies to the PSW as well as the GPRs. For the former register, the LSI-11 introduced MTPS and MFPS (move to/from processor status). Obviously, there was no need for extra instructions for getting at the GPRs....

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